(kicad_pcb
	(version 20260206)
	(generator "pcbnew")
	(generator_version "10.0")
	(general
		(thickness 1.6)
		(legacy_teardrops no)
	)
	(paper "A4")
	(layers
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		(9 "F.Adhes" user "F.Adhesive")
		(11 "B.Adhes" user "B.Adhesive")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
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		(7 "B.SilkS" user "B.Silkscreen")
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		(17 "Dwgs.User" user "User.Drawings")
		(19 "Cmts.User" user "User.Comments")
		(21 "Eco1.User" user "User.Eco1")
		(23 "Eco2.User" user "User.Eco2")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
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		(39 "User.1" user)
		(41 "User.2" user)
		(43 "User.3" user)
		(45 "User.4" user)
	)
	(setup
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				(type "Top Silk Screen")
			)
			(layer "F.Paste"
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			)
			(layer "F.Mask"
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				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
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				(thickness 1.51)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
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				(thickness 0.035)
			)
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				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
			)
			(copper_finish "None")
			(dielectric_constraints no)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(tenting
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			(back yes)
		)
		(covering
			(front no)
			(back no)
		)
		(plugging
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			(back no)
		)
		(capping no)
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		(zone_defaults)
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			(creategerberjobfile yes)
			(dashed_line_dash_ratio 12)
			(dashed_line_gap_ratio 3)
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			(plotframeref no)
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			(useauxorigin no)
			(pdf_front_fp_property_popups yes)
			(pdf_back_fp_property_popups yes)
			(pdf_metadata yes)
			(pdf_single_document no)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
			(dxfusepcbnewfont yes)
			(psnegative no)
			(psa4output no)
			(plot_black_and_white yes)
			(sketchpadsonfab no)
			(plotpadnumbers no)
			(hidednponfab no)
			(sketchdnponfab yes)
			(crossoutdnponfab yes)
			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 1)
			(scaleselection 1)
			(outputdirectory "")
		)
	)
	(footprint "EnvNode-Footprints:ORingPower_Module_Castellated"
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		(descr "EnvNode ORing Power module-side interface, 39 x 15 mm PCB, five castellated edge pads")
		(tags "EnvNode ORing Power module castellated half hole")
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		(units
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			(property pad_prop_castellated)
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			(property pad_prop_castellated)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "+3V3_EXT")
			(pinfunction "+3V3_EXT_3")
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			(uuid "62c7b906-ca0e-447f-a65b-362e75de8356")
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			(property pad_prop_castellated)
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			(remove_unused_layers no)
			(net "+3V3_DEVKIT")
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			(uuid "3d36f088-392a-46fc-a92a-88a604719b23")
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		(pad "5" thru_hole circle
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